1. Field of the Invention
This invention relates to memory test engines for dynamic random access memories, and particularly to a memory built-in self test apparatus and method with a trigger on failure and multiple patterns per load capability.
2. Description of Background
As chips become faster in frequency, there is a greater need for hardware to include self test logic that can validate internal logic, interconnects, and externally connected arrays of memory during all phases of the lifetime of a product. In the past, this testing has been performed by very expensive high-speed test equipment that requires a great deal of special test programs be written. Oftentimes when a fail occurs, the failing component is re-tested on a tester, and sometimes the fail is not able to be found due to the nature of the test programs (i.e., the way in which commands are sent). The cost of using high speed test equipment can be offset by designing self test logic into the chip.
The design of memory built in self test (MBIST) logic solves the problem of determining whether or not an array of memory connected to an interface chip is functional or not and may further help to isolate the failure to locations in the memory array. However, while the MBIST resolves some problems, other issues are left unresolved, such as, for example, capabilities for generating a memory controller type command stream to the memory array, reducing the number of times the MBIST engine must be configured per address load, creating a signal that external test equipment can use to trigger on a fail, testing a memory array with more than one address port, varying chip configurations dynamically during an MBIST run to generate AC pass/fail data, snooping a command stream to detect resource faults, and detecting address failures when reading back data with ECC encoded.